As device size is getting smaller at the 14 nm technology node, the complexity in manufacturing is increasing. The cost to produce the semiconductor devices is also increasing and cost effective solutions and innovations are needed. As smaller transistors are manufactured, the critical dimension (CD) or resolution of patterned features is becoming more challenging to produce. Self-aligned patterning may replace overlay-driven patterning so that cost-effective scaling can continue even after EUV introduction. Patterning options that enable reduced variability, extend scaling and enhanced CD and process control are needed. Selective deposition of thin films is a key step in patterning in highly scaled technology nodes. New deposition methods are required that provide selective film deposition on different material surfaces. The new methods that are needed include selective deposition of dielectric materials on dielectric materials (DoD), dielectric materials on metals (DoM), metals on metals (MoM), metals on dielectric materials (MoD), and metals on silicon (MOS).